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| IRF9510 Data Sheet July 1999 File Number 2214.4 3.0A, 100V, 1.200 Ohm, P-Channel Power MOSFET [ /Title (IRF95 10) /Subject (.0A, 00V, .200 hm, -Chanel ower OSET) /Autho () /Keyords Interil orpoation, -Chanel ower OSET, O20AB /Cretor () /DOCI FO dfark This P-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17541. Features * 3.0A, 100V * rDS(ON) = 1.200 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance Symbol D Ordering Information PART NUMBER IRF9510 PACKAGE TO-220AB BRAND IRF9510 G S NOTE: When ordering, include the entire part number. Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 5-3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRF9510 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRF9510 -100 -100 -3.0 -2.0 -12 20 20 0.16 190 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IGSS IDSS ID(ON) rDS(ON) gfs td(ON) tr td(OFF) tf TEST CONDITIONS VGS = 0V, ID = -250A, (Figure 10) VGS = VDS, ID = -250A VGS = 20V VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC VDS > ID(ON) x rDS(ON)MAX, VGS = -10V, (Figure 7) VGS = -10V, ID = -1.5A, (Figures 8, 9) VDS > ID(ON) x rDS(ON) Max, ID = -1.5A, (Figure 12) VDD = 0.5 x Rated BVDSS, ID -3.0A, RG = 50, VGS = 10V, (Figures 17, 18) RL = 15.7 for VDSS = 50V RL = 12.3 for VDSS = 40V MOSFET Switching Times are Essentially Independent of Operating Temperature VGS = -10V, ID = -3A, VDS = 0.8 x Rated BVDSS, (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = -25V, f = 1.0MHz, (Figure 11) MIN -100 -2.0 -3.0 0.8 TYP 1.000 1.1 15 30 20 20 MAX -4.0 100 -25 -250 1.200 30 60 40 40 UNITS V V nA A A A S ns ns ns ns Drain to Source Breakdown Voltage Gate to Threshold Voltage Gate to Source Leakage Current Zero-Gate Voltage Drain Current On-State Drain Current (Note 2) Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Drain Inductance Qg(TOT) Qgs Qgd CISS COSS CRSS LD - 8.5 3.8 4.7 180 85 30 3.5 11 - nC nC nC pF pF pF nH Measured From the Contact Screw on Tab to Center of Die Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S - 4.5 - nH Internal Source Inductance LS Measured From The Source Lead, 6mm (0.25in) From Header to Source Bonding Pad Typical Socket Mount - 7.5 - nH Junction to Case Junction to Ambient RJC RJA - - 6.4 62.5 oC/W oC/W 5-4 IRF9510 Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode G D MIN - TYP - MAX -3.0 -12 UNITS A A S Source to Drain Diode Voltage(Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES: VSD trr QRR TC = 25oC, ISD = -3.0A, VGS = 0V, (Figure 13) TJ = 150oC, ISD = -3.0A, dISD/dt = 100A/s TJ = 150oC, ISD = -3.0A, dISD/dt = 100A/s - 120 6.0 -1.5 - V ns C 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 25V, starting TJ = 25oC, L = 31.7mH, RG = 25, peak IAS = 3.0A. See Figures 15, 16. Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 Unless Otherwise Specified -5 ID, DRAIN CURRENT (A) -4 -3 0.6 0.4 -2 0.2 0 0 25 50 75 100 TC, CASE TEMPERATURE (oC) 125 150 -1 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE 1 0.5 PDM 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE t1 t2 NOTES: DUTY FACTOR: D = t1/t2 TJ = PDM x ZJC x RJC + TC 10-3 10-2 0.1 1 10 0.01 10-5 10-4 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE 5-5 IRF9510 Typical Performance Curves Unless Otherwise Specified (Continued) -5 10s 10 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 100s -4 VGS = -9V VGS = -10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -3 VGS = -8V 1ms 1 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) TC = 25oC TJ = MAX RATED 10ms 100ms DC -2 VGS = -7V VGS = -6V VGS = -5V -1 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 102 0 0 -10 -20 -30 -40 VDS, DRAIN TO SOURCE VOLTAGE (V) -50 FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS -5 ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -10V VGS = -9V -12.0 VDS > ID(ON) x RDS(ON)MAX. PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) -4 -9.6 -3 VGS = -8V -7.2 TJ = 125oC -4.8 TJ = 25oC TJ = -55oC -2 VGS = -7V VGS = -6V VGS = -5V -1 -2.4 0 0 -2 -4 -6 -8 -10 0 0 VDS, DRAIN TO SOURCE VOLTAGE (V) -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) -10 FIGURE 6. SATURATION CHARACTERISTICS rDS(ON), DRAIN TO SOURCE ON RESISTANCE FIGURE 7. TRANSFER CHARACTERISTICS 5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 4 2.5 2.0 VGS = -10V, ID = -1.5A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 3 VGS = -10V 2 VGS = -20V 1 1.5 1.0 0.5 0 0 -4 -8 -12 ID, DRAIN CURRENT (A) -16 -20 0 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 5-6 IRF9510 Typical Performance Curves 1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE Unless Otherwise Specified (Continued) 500 1.15 C, CAPACITANCE (pF) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD 400 COSS CDS + CGD 1.05 300 CISS 0.95 200 0.85 100 COSS CRSS 0.75 -40 0 40 80 120 160 0 0 -10 -20 -30 -40 -50 TJ, JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 2.5 gfs, TRANSCONDUCTANCE (S) TJ = -55oC 2.0 TJ = 25oC TJ = 125oC 1.5 ISD, SOURCE TO DRAIN CURRENT (A) -102 -10 TJ = 150oC TJ = 25oC -1 1.0 0.5 VDS > ID(ON) x RDS(ON) MAX. 80s PULSE TEST 0 -1.2 -2.4 -3.6 ID, DRAIN CURRENT (A) -4.8 -6.0 0 -0.1 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 VSD, SOURCE TO DRAIN VOLTAGE (V) -1.8 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 0 VGS, GATE TO SOURCE VOLTAGE (V) ID = -4A -5 -10 VDS = -20V VDS = -50V VDS = -80V -15 0 2 4 6 8 Qg(TOT), TOTAL GATE CHARGE (nC) 10 FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5-7 IRF9510 Test Circuits and Waveforms VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0 + VDD VDD 0V VGS DUT tP IAS 0.01 IAS tP BVDSS VDS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON td(ON) tr RL 0 10% tOFF td(OFF) tf 10% DUT VGS RG VDD + VDS VGS 0 90% 90% 10% 50% PULSE WIDTH 90% 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT -VDS (ISOLATED SUPPLY) 0 DUT 12V BATTERY 0.2F 50k 0.3F FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR VDS Qgs D G 0 IG(REF) IG CURRENT SAMPLING RESISTOR S +VDS ID CURRENT SAMPLING RESISTOR 0 DUT VDD Qgd Qg(TOT) VGS IG(REF) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS 5-8 IRF9510 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 5-9 |
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